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128m gddr sdram k4d263238i-vc - 1 - rev. 1.3 november 2006 128mbit gddr sdram revision 1.3 november 2006 * samsung electronics reserves the right to change products or specification without notice. notice information in this document is provid ed in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for us e in life support, critical care, m edical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any government al procurement to which special terms or provisions may apply.
128m gddr sdram k4d263238i-vc - 2 - rev. 1.3 november 2006 revision history revision month year history 0.0 may 2005 - target spec - defined target specification 0.1 september 2005 - added current spec - added ibis spec 1.0 october 2005 - finalized spec 1.1 december 2005 - change from trrd=15 ns / twr=20ns to trrd= 10ns / twr=15ns for -vc40(250mhz) 1.2 january 2006 - modified icc6 value from 7ma to 10ma 1.3 november 2006 - corrected typo
128m gddr sdram k4d263238i-vc - 3 - rev. 1.3 november 2006 the k4d263238i is 134,217,728 bits of hyper synchronous da ta rate dynamic ram organized as 4 x 1,048,576 words by 32 bits, fabricated with samsung s high performance cmos technology. synchronous features with data strobe allow extremely high performance up to 2.0gb/s/chip. i/o transactions are possible on bo th edges of the clock cycle. range of operating frequencies, programmable burst length and programma ble latencies allow the device to be useful for a variety of high performance memo ry system applications. ? 2.5v 5% power supply for device operation ? 2.5v 5% power supply for i/o interface ? sstl_2 compatible inputs/outputs ? 4 banks operation ? mrs cycle with address key programs -. read latency 3 (clock) -. burst length (2, 4, 8 and full page) -. burst type (sequential & interleave) ? full page burst length for sequential burst type only ? start address of the full page burst should be even ? all inputs except data & dm are sampled at the positive going edge of the system clock ? differential clock input ? write interrupted by read function general description features ? data i/o transactions on both edges of data strobe ? dll aligns dq and dqs transitions with clock transition ? edge aligned data & data strobe output ? center aligned data & data strobe input ? dm for write masking only ? auto & self refresh ? 32ms refresh period (4k cycle) ? 144pin fbga package ? maximum clock frequency up to 250mhz ? maximum data rate up to 500mbps/pin for 1m x 32bit x 4 bank ddr sdram 1m x 32bit x 4 banks double data rate sy nchronous dram with bi-directional da ta strobe and dll ordering information k4d263238i-vc is the lead free package part number. part no. max freq. max data rate interface package k4d263238i-vc40 250mhz 500mbps/pin sstl_2 144fbga k4d263238i-vc50 200mhz 400mbps/pin
128m gddr sdram k4d263238i-vc - 4 - rev. 1.3 november 2006 pin configuration (top view) pin description ck,ck differential clock input ba 0 , ba 1 bank select address cke clock enable a 0 ~a 11 address input cs chip select dq 0 ~ dq 31 data input/output ras row address strobe v dd power cas column address strobe v ss ground we write enable v ddq power for dq ? s dqs data strobe v ssq ground for dq ? s dm data mask nc no connection rfu reserved for future use mcl must connect low dqs0 vss rfu 1 thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vss vss vss vss vss vss vss vss vss rfu 2 a5 a6 dq4 dq6 dq7 dq17 dq19 dqs2 dq21 dq22 cas ras cs dm0 vddq dq5 vddq dq16 dq18 dm2 dq20 dq23 we nc nc nc vdd vddq vddq nc vddq vddq vdd nc ba0 ba1 a0 dq3 vddq dq31 dq1 a10 a2 a1 vdd vdd vdd dq2 vddq vdd a11 a3 a9 a4 dq0 vddq vdd dq29 dq30 dq28 vddq nc vss a7 vddq vddq nc vddq vddq vdd ck a8/ap dm3 vddq dq26 vddq dq15 dq13 dm1 dq11 dq9 nc ck cke dqs3 dq27 dq25 dq24 dq14 dq12 dqs1 dq10 dq8 nc vref 2345678910111213 b c d e f g h j k l m n note: 1. rfu1 is reserved for a12 2. rfu2 is reserved for ba2 3. vss thermal balls are optional mcl
128m gddr sdram k4d263238i-vc - 5 - rev. 1.3 november 2006 input/output functional description *1 : the timing reference point for the differ ential clocking is the cr oss point of ck and ck . for any applications us ing the single ended clocking, apply v ref to ck pin. symbol type function ck, ck *1 input the differential system clock input. all of the inputs are sampled on the rising edge of the clock except dq s and dm s that are sampled on both edges of the dqs. cke input activates the ck signal when high and deactivates the ck signal when low. by deactivating the clock, cke low indicates the power down mode or self refresh mode. cs input cs enables the command decoder when low and disabled the com- mand decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras input latches row addresses on the positive going edge of the ck with ras low. enables row access & precharge. cas input latches column addresses on the positive going edge of the ck with cas low. enables column access. we input enables write operation and row precharge. latches data in starting from cas , we active. dqs input/output data input and output ar e synchronized with both edge of dqs. dm 0 ~ dm 3 input data in mask. data in is masked by dm latency=0 when dm is high in burst write. dm 0 for dq 0 ~ dq 7, dm 1 for dq 8 ~ dq 15, dm 2 for dq 16 ~ dq 23, dm 3 for dq 24 ~ dq 31. dq 0 ~ dq 31 input/output data inputs/outputs are multiplexed on the same pins. ba 0 , ba 1 input selects which bank is to be active. a 0 ~ a 11 input row/column addresses are multiplexed on the same pins. row addresses : ra 0 ~ ra 11 , column addresses : ca 0 ~ ca 7 . column address ca 8 is used for auto precharge. v dd /v ss power supply power and ground for the input buffers and core logic. v ddq /v ssq power supply isolated power supply and ground for the output buffers to provide improved noise immunity. v ref power supply reference voltage for inputs, used for sstl interface. mcl must connect low must connect low
128m gddr sdram k4d263238i-vc - 6 - rev. 1.3 november 2006 block diagram (1mbit x 32i/o x 4 bank) bank select timing register address register refresh counter row buffer row decoder col. buffer data input register serial to parallel 1mx32 1mx32 1mx32 1mx32 sense amp 2-bit prefetch output buffer i/o control column decoder latency & burst length programming register strobe gen. ck,ck addr lcke ck,ck cke cs ras cas we dmi ldmi ck,ck lcas lras lcbr lwe lwcbr lras lcbr ck, ck 64 64 32 32 lwe ldmi x32 dqi data strobe intput buffer dll
128m gddr sdram k4d263238i-vc - 7 - rev. 1.3 november 2006 ? power-up sequence ddr sdrams must be powered up and initialized in a predefined manner to prevent undefined operations. 1. apply power and keep cke at low state (all other inputs may be undefined) - apply vdd before vddq . - apply vddq before vref & vtt 2. start clock and maintain stable condition for minimum 200us. 3. the minimum of 200us after stable power and clock(ck,ck ), apply nop and take cke to be high. 4. issue precharge command for all banks of the device. 5. issue a emrs command to enable dll *1 6. issue a mrs command to reset dll. the additional 200 clock cycles are required to lock the dll. * 1,2 7. issue precharge command for all banks of the device. 8. issue at least 2 or more auto-refresh commands. 9. issue a mode register set command with a8 to low to initialize the mode register. *1 the additional 200cycles of clock input is required to lock the dll after ena bling dll. *2 sequence of 6&7 is regardless of the order. functional description power up & initialization sequence command 0 12345678910111213141516171819 trp 2 clock min. precharge all banks 2nd auto refresh mode register set any command t rfc 1st auto refresh t rfc emrs mrs 2 clock min. dll reset precharge all banks t rp ck ck inputs must be stable for 200us 200 clock min. 2 clock min. * when the operating frequency is change d, dll reset should be required again. after dll reset again, the mini mum 200 cycles of clock input is needed to lock the dll.
128m gddr sdram k4d263238i-vc - 8 - rev. 1.3 november 2006 the mode register stores the data for controlling the vari ous operating modes of ddr sdram. it programs cas latency, addressing mode, burst length, test mode, dll reset and vari ous vendor specific options to make ddr sdram useful for variety of different applications. the default value of the mode register is not defi ned, therefore the mode register must be written after emrs setting for proper operation. th e mode register is written by asserting low on cs , ras , cas and we (the ddr sdram should be in active mode with cke already hi gh prior to writing into t he mode register). the state of address pins a 0 ~ a 11 and ba 0 , ba 1 in the same cycle as cs , ras , cas and we going low is written in the mode register. minimum two clock cycles are requ ested to complete the write op eration in the mode register. the mode register contents can be changed using the same command and clock cycle requirements du ring operation as long as all banks are in the idle state. the mode register is divided into various fields depending on functionality. the burst length uses a 0 ~ a 2 , addressing mode uses a 3 , cas latency(read latency from column address) uses a 4 ~ a 6 . a 7 is used for test mode. a 8 is used for dll reset. a 7, a 8 , ba 0 and ba 1 must be set to low for normal mrs operation. refer to the table for specific codes for various burst length, addre ssing modes and cas latencies. mode register set(mrs) address bus mode cas latency a 6 a 5 a 4 latency 000 reserved 001 reserved 010 reserved 011 3 100 reserved 101 reserved 110 reserved 111 reserved burst length a 2 a 1 a 0 burst type sequential interleave 0 0 0 reserve reserve 001 2 2 010 4 4 011 8 8 1 0 0 reserve reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 full page reserve burst type a 3 type 0 sequential 1 interleave * rfu(reserved for future use) should stay "0" during mrs cycle. mrs cycle command *1: mrs can be issued only at all banks precharge state. *2: minimum t rp is required to issue mrs command. 0 ck, ck precharge nop nop mrs nop nop 2 01 5 34 8 67 any nop all banks command t rp t mrd =2 t ck ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 rfu 0 rfu dll tm cas latency bt burst length ba 0 a n ~ a 0 0mrs 1emrs dll a 8 dll reset 0no 1yes test mode a 7 mode 0 normal 1test register nop
128m gddr sdram k4d263238i-vc - 9 - rev. 1.3 november 2006 the extended mode register stores the data for enabling or disabling dll and selecting output driver strength. the default value of the extended mode register is not defined, th erefore the extend mode register must be written after power up for enabling or disabling dll. the extended mode register is written by asserting low on cs , ras , cas , we and high on ba0(the ddr sdram should be in all bank precharge with cke already high prior to writing into the extended mode register). the stat e of address pins a0, a2 ~ a5, a7 ~ a11 and ba1 in the same cycle as cs , ras , cas and we going low are written in the extended mode register. a1 and a6 are us ed for setting driver strength to weak or matched imped- ance. two clock cycles are required to co mplete the writ e operation in the ex tended mode register . the mode register contents can be changed usin g the same command an d clock cycle requirements during operation as lo ng as all banks are in the idle state. a0 is used for dll enable or disable. ?high? on ba0 is used for emrs. all the other address pins except a0,a1,a6 and ba0 must be set to low for proper emrs operation. refer to the table for specific codes. a 0 dll enable 0 enable 1 disable ba 0 a n ~ a 0 0mrs 1emrs figure 7. extend mode register set extended mode register set(emrs) address bus extended ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 rfu 1 rfu d.i.c rfu d.i.c dll mode register * rfu(reserved for future use) should stay "0" during emrs cycle. a 6 a 1 output driver impedance control 00 full 100% 01 weak 60% 10 n/a do not use 11 matched 30%
128m gddr sdram k4d263238i-vc - 10 - rev. 1.3 november 2006 pull up -120 -100 -80 -60 -40 -20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 voltage (v) current (ma ) 100% min 100% max 60% min 60% max 30% min 30% max voltage 100% min 100% max 60% min 60% max 30% min 30% max 00 0 0000 0.1 -5.688 -8.096 -5.076 -7.216 -3.672 -5.148 0.2 -11.232 -15.796 -9.936 -14.168 -7.2 -10.34 0.3 -16.596 -23.496 -14.544 -20.988 -10.548 -15.224 0.4 -21.636 -31.108 -19.08 -27.72 -13.752 -20.02 0.5 -26.64 -38.28 -23.256 -34.1 -16.776 -24.64 0.6 -31.14 -45.144 -27.216 -40.26 -19.584 -29.04 0.7 -35.496 -51.92 -30.924 -46.288 -22.212 -33.352 0.8 -39.456 -58.344 -34.344 -51.832 -24.66 -37.4 0.9 -43.128 -64.372 -37.404 -57.156 -26.856 -41.184 1 -46.224 -70.224 -40.104 -62.304 -28.728 -44.792 1.1 -48.996 -75.636 -42.408 -66.836 -30.456 -48.004 1.2 -51.336 -80.52 -44.352 -71.016 -31.86 -51.04 1.3 -53.244 -85.052 -45.972 -74.844 -33.048 -53.724 1.4 -54.828 -88.968 -47.304 -78.232 -33.984 -55.968 1.5 -56.088 -92.224 -48.384 -81.136 -34.812 -58.08 1.6 -57.168 -94.919 -49.284 -83.6 -35.496 -59.84 1.7 -58.104 -96.844 -50.04 -85.756 -36.072 -61.292 1.8 -58.86 -99.187 -50.724 -87.472 -36.612 -62.524 1.9 -59.616 -100.562 -51.3 -88.924 -36.873 -63.668 2 -60.228 -101.893 -51.84 -89.617 -37.152 -64.504 2.1 -60.84 -102.63 -52.344 -90.849 -37.53 -65.34 2.2 -61.38 -103.411 -52.776 -91.564 -37.773 -65.956 2.3 -61.497 -104.544 -53.181 -92.037 -37.989 -66.66 2.4 -61.821 -105.303 -53.487 -92.774 -38.385 -67.232 2.5 -61.947 -105.644 -53.631 -92.807 -38.781 -67.76 2.6 -62.01 -106.392 -53.64 -93.06 -38.853 -68.244 2.7 -62.208 -106.392 -53.694 -93.126 -38.988 -68.684 pullup current(ma) pullup current(ma) pullup current(ma) ibis : pull up
128m gddr sdram k4d263238i-vc - 11 - rev. 1.3 november 2006 voltage 100% min 100% max 60% min 60% max 30% min 30% max 00 0 0000 0.1 6.984 9.1795 6.048 8.624 3.708 5.28 0.2 13.86 17.193 12.132 17.16 7.38 10.56 0.3 20.448 25.036 17.748 25.388 10.836 15.532 0.4 26.82 32.714 23.256 33.616 14.076 20.68 0.5 32.832 40.205 28.476 41.404 17.172 25.3 0.6 38.484 47.487 33.336 49.104 19.944 30.096 0.7 43.632 54.538 37.908 56.628 22.5 34.408 0.8 48.384 61.347 41.976 63.492 24.624 38.5 0.9 52.56 67.881 45.432 70.18 26.424 42.196 1 56.088 74.129 48.348 76.208 27.828 45.452 1.1 58.896 80.058 50.688 81.532 28.908 48.18 1.2 61.02 85.635 52.452 86.196 29.664 50.468 1.3 62.604 90.816 53.748 90.2 30.24 52.228 1.4 63.756 95.568 54.684 93.841 30.672 53.548 1.5 64.548 99.825 55.332 96.481 30.924 54.604 1.6 65.124 103.532 55.8 98.34 31.212 55.352 1.7 65.628 106.579 56.232 99.077 31.356 55.924 1.8 65.988 108.922 56.52 100.177 31.536 56.32 1.9 66.312 110.66 56.808 100.782 31.68 56.628 2 66.6 112.002 57.06 101.167 31.824 56.892 2.1 66.816 112.992 57.312 101.552 31.932 57.156 2.2 67.068 113.762 57.456 101.739 32.076 57.376 2.3 67.284 114.422 57.636 102.245 32.184 57.508 2.4 67.464 115.082 57.852 102.553 32.292 57.728 2.5 67.608 115.632 58.032 102.828 32.364 57.816 2.6 67.824 116.072 58.176 102.861 32.436 57.992 2.7 67.968 116.512 58.32 102.905 32.58 58.124 pulldown current(ma) pulldown current(ma) pulldown current(ma) pull down 0 20 40 60 80 100 120 140 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 voltage (v) current (ma ) 100% min 100% max 60% min 60% max 30% min 30% max ibis : pull down
128m gddr sdram k4d263238i-vc - 12 - rev. 1.3 november 2006 absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd -1.0 ~ 3.6 v voltage on v dd supply relative to vss v ddq -0.5 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.8 w short circuit current i os 50 ma permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restri cted to recommended operating condition. exposure to higher than recommended voltage for extended per iods of time could affect device reliability. note : power & dc operating conditions(sstl_2 in/out) recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 65 c) parameter symbol min typ max unit note device supply voltage v dd 2.375 2.50 2.625 v 1 output supply voltage v ddq 2.375 2.50 2.625 v 1 reference voltage v ref 0.49*v ddq - 0.51*v ddq v2 termination voltage vtt v ref -0.04 v ref v ref +0.04 v 3 input logic high voltage v ih v ref +0.15 - v ddq +0.30 v 4 input logic low voltage v il -0.30 - v ref -0.15 v 5 output logic high voltage v oh vtt+0.76 - - v i oh =-15.2ma output logic low voltage v ol - - vtt-0.76 v i ol =+15.2ma input leakage current i il -5 - 5 ua 6 output leakage current i ol -5 - 5 ua 6 1. under all conditions v ddq must be less than or equal to v dd . 2. v ref is expected to equal 0.50*v ddq of the transmitting device and to track variations in the dc level of the same. peak to peak noise on the v ref may not exceed + 2% of the dc value. thus, from 0.50*v ddq , v ref is allowed + 25mv for dc error and an additional + 25mv for ac noise. 3. v tt of the transmitting device must track v ref of the receiving device. 4. v ih (max.)= v ddq +1.5v for a pulse and it which can not be greater than 1/3 of the cycle rate. 5. v il (min.)= -1.5v for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. for any pin under test input of 0v v in v dd is acceptable. for all other pins that are not under test v in =0v. note :
128m gddr sdram k4d263238i-vc - 13 - rev. 1.3 november 2006 dc characteristics note: 1. measured with outputs open. 2. refresh period is 32ms. parameter symbol test condition version unit note -40 -50 operating current (one bank active) i cc1 burst lenth=2 t rc t rc (min) i ol =0ma, t cc = t cc (min) 189 170 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = t cc (min) 11 11 ma precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), t cc = t cc (min). 48 43 ma active standby current power-down mode i cc3 p cke v il (max), t cc = t cc (min) 78 67 ma active standby current in in non power-down mode i cc3 n cke vih(min), cs vih(min), t cc = t cc (min) . 153 134 ma operating current ( burst mode) i cc4 i ol =0ma , t cc = t cc (min), page burst, all banks activated. 402 344 ma refresh current i cc5 t rc t rfc (min) 159 135 ma 2 self refresh current i cc6 cke 0.2v 10 ma recommended operating conditions unless otherwise noted, t a =0 to 65 c) ac input operating conditions recommended operating conditions(voltage referenced to v ss =0v, v dd / v ddq =2.5v+ 5% , t a =0 to 65 c) parameter symbol min typ max unit note input high (logic 1) voltage; dq v ih v ref +0.35 - - v input low (logic 0) voltage; dq v il --v ref -0.35 v clock input differential voltage; ck and ck v id 0.7 - v ddq +0.6 v 1 clock input crossing point voltage; ck and ck v ix 0.5*v ddq -0.2 - 0.5*v ddq +0.2 v 2 1. v id is the magnitude of the diff erence between the input level on ck and the input level on ck 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track va riations in the dc level of the same note :
128m gddr sdram k4d263238i-vc - 14 - rev. 1.3 november 2006 ac operating test conditions ( v dd / v ddq =2.5v+ 5% , t a = 0 to 65 c) parameter value unit note input reference voltage for ck(for single ended) 0.50*v ddq v ck and ck signal maximum peak swing 1.5 v ck signal minimum slew rate 1.0 v/ns input levels(v ih /v il )v ref +0.35/v ref -0.35 v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see fig.1 r t =50 ? output c load =30pf (fig. 1) output load circuit z0=50 ? v ref =0.5*v ddq v tt =0.5*v ddq decoupling capacitance guide line recommended decoupling capacitance added to power line at board. parameter symbol value unit decoupling capacitance between v dd and v ss c dc1 0.1 + 0.01 uf decoupling capacitance between v ddq and v ssq c dc2 0.1 + 0.01 uf 1. v dd and v ddq pins are separated each other. all v dd pins are connected in chip. all v ddq pins are connected in chip. 2. v ss and v ssq pins are separated each other all v ss pins are connected in chip. all v ssq pins are connected in chip. note : capacitance (v dd =2.5v, t a = 25 c, f=1mhz) parameter symbol min max unit input capacitance( ck, ck )c in1 1.0 5.0 pf input capacitance(a 0 ~a 11 , ba 0 ~ba 1 )c in2 1.0 4.0 pf input capacitance ( cke, cs , ras ,cas , we ) c in3 1.0 4.0 pf data & dqs input/output capacitance(dq 0 ~dq 31 )c out 1.0 6.0 pf input capacitance(dm0 ~ dm3) c in4 1.0 6.0 pf
128m gddr sdram k4d263238i-vc - 15 - rev. 1.3 november 2006 13467 tcl tck hi-z hi-z ck, ck dqs dq cs dm 25 tis tih 8 tds tdh 01 trpst trpre db0 db1 tdqss tdqsh tch da1 da2 twpst command reada writeb tdqsq t wpres t wpreh tdqsck tac ac characteristics simplified timing @ bl=2, cl=3 parameter symbol -40 -50 unit note min max min max ck cycle time cl=3 tck 4.0 10 5.0 10 ns ck high level width tch 0.45 0.55 0.45 0.55 tck ck low level width tcl 0.45 0.55 0.45 0.55 tck dqs out access time from ck tdqsck -0.6 0.6 -0.7 +0.7 ns output access time from ck tac -0.6 0.6 -0.7 +0.7 ns data strobe edge to dout edge tdqsq - 0.4 - +0.45 ns read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.85 1.15 0.8 1.2 tck dqs-in setup time twpres 0 - 0 - ns dqs-in hold time twpreh 0.35 - 0.25 - tck dqs write postamble twpst 0.4 0.6 0.4 0.6 tck dqs-in high level width tdqsh 0.4 0.6 0.4 0.6 tck dqs-in low level width tdqsl 0.4 0.6 0.4 0.6 tck address and control input setup tis 0.9 - 1.0 - ns address and control input hold tih 0.9 - 1.0 - ns dq and dm setup time to dqs tds 0.4 - 0.45 - ns dq and dm hold time to dqs tdh 0.4 - 0.45 - ns clock half period thp tclmin or tchmin - tclmin or tchmin -ns data output hold time from dqs tqh thp-0.4 - thp-0.45 - ns
128m gddr sdram k4d263238i-vc - 16 - rev. 1.3 november 2006 note 1 : - the jedec ddr specification currently defines the output data va lid window(tdv) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - the previously used definiti on of tdv(=0.35tck) artificially penalizes system timing budgets by assuming the worst case output valid window even then the clock duty cycle applie d to the device is better than 45/55% - a new ac timing term, tqh which stands for data output hold time from dqs is defined to a ccount for clock duty cycle variation and replaces tdv - tqhmin = thp-x where . thp=minimum half clock period fo r any given cycle and is de fined by clock high or clock low time(tch,tcl) . x=a frequency dependent timing allowance account for tdqsqmax tqh timing (cl3, bl2) 134 thp ck, ck dqs dq cs 25 01 command reada tqh da0 tdqsq(max) tdqsq(max) da1
128m gddr sdram k4d263238i-vc - 17 - rev. 1.3 november 2006 ac characteristics (i) note : 1. for normal write operation, even numbers of din are to be written inside dram 2. the number of clock of trp is restricted by the number of clock of tras and trp 3. the number of clock of twr_a is fixed. it can?t be changed by tck 4. trcdwr is equal to trcdrd-2tck and the number of clock can not be lower than 2tck. 5. the minimum number of clock cycles is dete rmined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer unconditionally. parameter symbol -40 -50 unit note min max min max row cycle time trc 48 - 50 - ns 2,5 refresh row cycle time trfc 56 - 55 - ns 5 row active time tras 32 100k 35 100k ns 5 ras to cas delay for read trcdrd 16 - 15 - ns 5 ras to cas delay for write trcdwr 8 10 ns 4 row precharge time trp 16 - 15 - ns 5 row active to row active trrd 10 - 10 - ns 5 last data in to row precharge twr 15 - 15 - ns 5 last data in to row precharge @auto precharge twr_a 3 - 3 - tck 3 auto precharge write recovery + pre- charge tdal 7 - 6 - tck 3,5 last data in to read command tcdlr 2 - 2 - tck 1 col. address to col. address tccd 1 - 1 - tck mode register set cycle time tmrd 2 - 2 - tck exit self refresh to read command txsr 200 - 200 - tck power down exit time tpdex 3tck+tis - 3tck+tis -ns refresh interval time tref - 7.8 - 7.8 us ac characteristics (ii) * 200/166mhz are supported in k4d263238i-vc40 * 166mhz is supported in k4d263238i-vc50 k4d263238i-vc40 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 250mhz ( 4.0ns ) 3 12 14 8 4 2 4 3 7 tck 200mhz ( 5.0ns ) 3 10 11 7 3 2 3 2 6 tck 166mhz ( 6.0ns ) 3 99632326tck k4d263238i-vc50 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 200mhz ( 5.0ns ) 3 10 11 7 3 2 3 2 6 tck 166mhz ( 6.0ns ) 3 99632326tck
128m gddr sdram k4d263238i-vc - 18 - rev. 1.3 november 2006 01 23 45 678 baa ra ra trcd activea activeb writea writeb db0 db1 db3 13 14 15 16 17 18 19 20 21 baa bab ca cb baa ca 9101112 prech baa 22 ra da0 da1 da2 da3 normal write burst (@ bl=4) multi bank interleaving write burst (@ bl=4) baa ra ra bab rb rb db2 tras trc trp trrd command dqs dq we dm ck, ck a8/ap addr (a0~a7, ba[1:0] a9~,a11) activea writea da0 da1 da2 da3 simplified timing(2) @ bl=4, cl=3
128m gddr sdram k4d263238i-vc - 19 - rev. 1.3 november 2006 package dimensions (144-ball fbga) unit : mm 12.0 12.0 0.8 0.8 0.35 0.05 1.40 max 0.45 0.05 0.8x11=8.8 0.40 0.8x11=8.8 0.40 b c d e f g h j k l m n 13 12 11 10 9 8 7 6 5 4 3 2 a1 index mark a1 index mark 0.10 max

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